SYNAPSE

Scientific background

Conventional non volatile (Flash) memories are inherently limited by relatively low speeds and endurances (set/reset cycles). These limitations can be overcome by Phase Change Memories (PCMs), made by chalcogenide materials, typically Ge2Sb2Te5 (GST), in which the programming function is based on the different electrical resistance offered by their amorphous and crystalline phases, that can reversibly be induced by proper current pulses [1,2,3,4,5]. Amorphization (reset) is obtained via a high intensity and short duration current pulse that melts the active region, followed by rapid quenching. The crystallization (set) process is induced by a longer duration and medium intensity current pulse, which anneals the active region.

Important issues for development and commercialization of PCMs in the near future are the increase of the storage capacity per cell and the reduction of the power consumption and costs. This can be achieved by reducing the size of the chalcogenide-based memory cells to the nano-scale, since lowering active material volumes to be programmed allows reducing power consumption and increases at the same time the cell density. Also, the scaling of the active material/bottom electrode contact area [6], cell confinement in trenches/pores [7] and 3D cross-bar architectures [8] are being explored. The ultimate programming energy reduction and fast switching have been obtained in Interfacial Phase Change memory (IPCM) by the use of ultra thin GeTe/Sb2Te3 superlattices [9]. To reduce the programming material volume, one viable route is the use of self-assembly processes to produce low-dimensional phase change materials for the cells. Nanostructured phase change chalcogenides have been obtained by different techniques, such as laser ablation [10], electron beam lithography on sputter deposited thin films [11], self assembling polymers [12] and chemically deposited by colloidal particles [13]. The possibility to use phase change nanowires offers the interesting possibility to exploit the scaling properties of PCM, since their growth can be controlled, along with their diameter, composition and crystallinity. A bottom-up self-assembly approach is attractive for growing phase change nanowires (NWs) [14] which are not damaged by the patterning processes, such as reactive ion etching (RIE). Growth of single-material (SM) and core-shell (CS) chalcogenide NWs by vapor transport methods has been reported; promising functionality tests are encouraging for the future NW implementation in PCMs, including multi-level devices exploiting CS-NWs [15]. The possibility to obtain multilevel PCM was already explored in thin films by M. Rozenberg et al. [16] with drawbacks related to poor control of the crystalline and amorphous states, a narrow programming window and unsatisfactory reproducibility. A multi-layer phase change material stack, formed by Nitrogen-doped GST and GST layers sandwiching a Ta2O5 barrier layer, was reported by Gyanathan et al [17], exhibiting a resistance window of one order of magnitude. The GST/GeTe CS-NWs by Jung et al. [15] demonstrated that the way to remove such limitations is to couple different phase change materials, featuring different electrical and thermal properties. Programming can be performed by acting on the crystalline/amorphous phases of the involved materials, exploiting low programming volumes, high cell density and defect-free nanostructures. Multilevel data encoding is therefore realized by introducing different offsets of phase transitions, in a core-shell/shell-core sequence, thus obtaining at least an intermediate, mixed resistive state, located between the high and the low resistive states of the core and shell materials. Of course, scaling down PCM cells from thin films to NWs requires specific solutions to different reliability problems related to the reduced length scale. As often occurs at the nanoscale, new physical effects, negligible at the larger length scale, arise and have to be taken into account. New possibilities are offered by advanced chemical deposition techniques, such as the Metal Organic Chemical Vapor Deposition (MOCVD), which allows high material compositional control, high purity, industrial scalability on 12” substrates and relatively high deposition rates. Nevertheless, there are very few reports available on the MOCVD of chalcogenide NWs [18,19,20] and none on CS-NWs by MOCVD. Besides the new ultrascaled device architectures that NWs enable, there is also a need for the development of new chalcogenide alloys. Memories based on GST have been demonstrated to exhibit 10 years retention for temperatures up to 110°C [21], which is sufficient for several applications, including mobile phone cards. However, for automotive applications the 10 years retention is required at the temperature of 125°C [22]. A higher retention temperature corresponds to a higher stability of the amorphous phase, and thus to a higher crystallization temperature. GST has a high melting temperature (T_M ≈ 620°C), but too low a crystallization temperature (T_X ≈ 160 °C), and insufficient multi-bit storage capability. In-based chalcogenide materials, namely those belonging to the In-Ge-Te and In-Sb-Te system, display higher thermal stability: In-Ge-Te (IGT) as a very high crystallization temperature (T_X ≈ 276°C) and very good 10-year retention at 170 °C [22,23], while In₃Sb₁Te₂ (IST) has an even higher crystallization temperature (T_X ≈ 280°C) [24]. The concept which will be explored in this project is the potential for using new core-shell nanowires formed by proper combinations of Ge-based and In-based phase change chalcogenides, synthesized by MOCVD, for the next generation of innovative memory cell design.

References

[1] W. Welnic, M. Wuttig, Mater. Today, 11 (2008) 20-27.
[2] S. Raoux, R. M. Shelby, J. Jordan-Sweet, B. Munoz, M. Salinga, Y.-C. Chen, Y.-H. Shih, E.-K. Lai, M.-H. Lee, Microelectron. Eng., 85 (2008), 2330-2333.
[3] R. Bez, Tech. Dig. – Int. Devices Meet., 2009, 89.
[4] M.Terao, T. Morikawa, T. Ohta, J. Journal of Appl. Phys., 48 (2009) 080001.
[5] A. L. Lacaita, D. J. Wouters, phys. stat. sol. (a), 205 (2008) 2281.
[6] Y.H. Ha, J.H. Yi, H. Horii, J.H. Park, S.H. Joo, S.O. Park, U-In Chung, J.T. Moon, in VLSI Symp. Tech. Dig., 2003, pp. 175-176.
[7] A. Pirovano, F. Pellizzer, I. Tortorelli, A. Riganò, R. Harrigan, M. Magistretti, P. Petruzza, E. Varesi, A. Redaelli, D. Erbetta, T. Marangon, F. Bedeschi, R. Fackenthal, G. Atwood, R. Bez, Solid- State Electronics 52 (2008) 1467-1472.
[8] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura and K. Torii, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 24-25.
[9] R. E. Simpson, P. Fons, A. V. Kolobov, T. Fukaya, M. Krbal, T. Yagi and J. Tominaga, Nat. Nanotechnol., 6 (2011) 501-505.
[10] D.-S. Suh, E. Lee, K. H. P. Kim, J.-S. Noh, W.-C. Shin, Y.-S. Kang, C. Kim, and Y. Khanga, Appl. Phys. Lett., 90 (2007) 023101.
[11] S. Raoux, C. T. Rettner, J. L. Jordan-Sweet, A. J. Kellock, T. Topuria, P. M. Rice, and D. C. Miller, J. Appl. Phys., 102 (2007) 094305.
[12] P. La Fata, R. Puglisi, S. Lombardo, C. Bongiorno, Superlattices and Microstructures, 44 (2008) 693-698.
[13] M. A. Caldwell, S. Raoux, R. Y. Wang, H.-S. P. Wong and D. J. Milliron, J. Mater. Chem., 20 (2010) 1285-1291.
[14] B. Yu, X. Sun, S. Ju, D. B. Janes, M. Meyyappan, IEEE Transactions on Nanotechnology, 7 (2008) 496-502.
[15] Y. Jung, S.-H. Lee, A.T. Jennings, R. Agarwal, Nano Lett., 8 (2008) 2056.
[16] M. J. Rozenberg, I. H. Inoue, and M. J. Sanchez, Phys. Rev. Lett., 92 (2004) 178302.
[17] A. Gyanathan and Y.-C. Yeo, J. Appl. Phys., 110 (2011) 124517.
[18] M. Longo, C. Wiemer, O. Salicio, M. Fanciulli, L. Lazzarini, E. Rotunno, J. Cryst. Growth, 315 (2011) 152.
[19] J.-K. Ahn, K.-W. Park, H.-J. Jung, S.-G. Yoon, Nano Lett., 10 (2010) 472-477.
[20] M. Longo, R. Fallica, C. Wiemer, O. Salicio, M. Fanciulli, E. Rotunno, L. Lazzarini Nano Lett., 12 (2012) 1509-1515.
[21] A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pelizzer, S. Hudgens and R. Bez., IEDM Tech. Dig., (2003).
[22] T. Morikawa, K. Kurotsuchi, M. Kinoshita, N. Matsuzaki, Y. Matsui, IEDM Tech. Dig., 307 (2007).
[23] Y.T. Kim, E.T. Kim, J.Y. Lee, Proceedings of the 13th WSEAS International Conference on CIRCUITS
[24] Y. Maeda, H. Andoh, I: Ikuta, H. Minemura, J. Appl. Phys., 64 (1988) 1715.